The present invention relates to mixer circuitry and to a method of operating mixer circuitry.
The prior art contains a number of examples of mixer circuitry for multiplying together two incoming signals to produce an output signal One known configuration of mixer circuitry contains a so-called xe2x80x9cGilbert cellxe2x80x9d. Gilbert cells consist of cross-coupled differential amplifiers composed of bipolar junction transistors. Typically, a first long tailed pair has loads formed by second and third differential pairs whose inputs and outputs are cross-coupled, the outputs being connected to a supply voltage via load resistors. The first long tailed pair has an emitter current source connected to a second supply voltage.
Such a mixer normally requires a minimum of three volts as its supply. This is because the Gilbert cellxe2x80x94assuming that the emitter current source is formed by a transistorxe2x80x94has three bipolar transistors connected across the supply voltage as well as series connected the load resistances. Attempts to reduce the supply voltage below three volts may result in transistors of the differential or long tailed pairs saturating, which has a number of disadvantageous effects. By saturation it is intended to mean providing a base voltage which is sufficiently higher than the collector voltage to cause conduction through the base-collector diode, ie. around 600 mV for a silicon transistor. Firstly, saturation entails an increase in base current. Secondly, capacitative effects cause the device to slow down.
It is accordingly an object of the present invention to at least partially mitigate the problems of the prior art.
According to a first aspect of the present invention there is provided a method of operating mixer circuitry, the mixer circuitry comprising a series circuit of the collector-emitter paths of first-third bipolar transistors, said first transistor having a collector forming one end of said circuit, the emitter of said second transistor being connected to the collector of said third transistor so that the collector voltage of said third transistor corresponds to the emitter voltage of the second transistor and said third transistor having an emitter forming a second end of said circuit, said series circuit being connected at said one end thereof via a first resistor to a supply potential and at said second thereof via a second resistor to a reference voltage, the method comprising:
providing a voltage drop across the first resistor, whereby said collector of said first transistor is at a potential between said supply potential and said reference voltage;
selecting a varying base voltage for application to a base of said first transistor, said base voltage having a maximum at least equal to said supply potential, being selected to provide a base-collector voltage at which conduction of the base-collector diode does not occur and having a minimum corresponding to a minimum voltage of said collector voltage of the second transistor;
providing a mixing base voltage to said second transistor, said mixing base voltage being selected to have a maximum level greater than the minimum collector voltage of said second transistor but less than a voltage at which the base-collector diode conducts, when the collector voltage is minimum, whereby the potential across said series circuit is less than three base-emitter voltages.
Preferably said third transistor is a dc bias transistor having a base terminal connected to receive a constant potential.
Advantageously said third transistor is a NPN device and has a base potential more than 500 mV above the collector potential.
Conveniently said step of providing a mixing base voltage comprises providing a varying voltage having a maximum and a minimum, the maximum being less than said supply voltage; offsetting said voltage by a predetermined amount toward said supply voltage whereby said offset voltage forms said mixing base voltage.
Conveniently again the method further comprises operating the third transistor in a saturated region at least when said mixing base voltage, and thereby the collector voltage of said third transistor, is minimum.
Advantageously said step of offsetting said voltage comprises providing said input voltage at one end of a resistor having a second end, providing a first constant current from said one end to said reference potential and providing a second constant current from said second end to said supply potential, wherein said second constant current is less than said first constant current.
Conveniently said second constant current is half said first constant current.
Preferably the method further comprises providing a varying input voltage at the base of an NPN transistor and deriving said voltage from an emitter of said transistor wherein said maximum of said input voltage corresponding substantially to the supply voltage.
Advantageously the method further comprises applying said second constant current to a diode as said constant potential of said dc bias transistor.
According to a second aspect of the present invention, there is provided a mixer circuitry comprising a series circuit of the collector-emitter paths of first-third bipolar transistors, said first transistor having a collector forming one end of said circuit and said third transistor having an emitter forming a second end of said circuit, the emitter of said second transistor being connected to the collector of said third transistor so that the collector voltage of said third transistor corresponds to the emitter voltage of the second transistor said series circuit being connected at said one end thereof via an output resistor to a supply potential and at said other end thereof via a bias resistor to reference voltage, the mixer circuitry having control circuitry connected to the base of said first transistor to provide a maximum potential on said base greater than the minimum collector voltage of said first transistor by an amount insufficient for conduction of the base-collector diode of said first transistor; mixing voltagexe2x80x94providing circuitry connected to the base of said second transistor, said mixing voltagexe2x80x94producing circuitry providing a maximum potential at the base of said second transistor, which is greater than the minimum collector voltage of said second transistor by an amount insufficient for conduction of the base-collector diode of said second transistor whereby the potential across said series circuit is less than three base-emitter voltages.
Preferably said third transistor is a dc bias transistor having a base terminal connected to receive a constant potential, and further comprising base-drive circuitry for operating the third transistor in a saturated region.
Advantageously said third transistor is a NPN device and said base drive circuitry has a base potential more than 500 mV above the minimum collector potential.
Preferably the mixer circuitry has an input for a voltage, and offset circuitry for offsetting said voltage by a predetermined amount toward said supply voltage, said offset circuitry having an output forming said mixing base voltage. conveniently the offsetting circuitry comprises a resistor having a first and a second end, said input being connected at said first end and a first constant current source being further connected to said first to said reference potential and a second constant current source connected from said second end to said supply potential, wherein said second constant current is less than said first constant current.
Advantageously said second constant current source provides half the current of said first constant current source
Conveniently said maximum of said input voltage corresponding substantially to the supply voltage.
Conveniently a diode is connected to the base of said dc bias transistor and receives the output of said second constant current source.